diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py
index 1c495eebbf77059b1c6433ff8064bd215dc8dca5..9b305e51444b7b28cd48698f084c9e7cd5a97b53 100644
--- a/src/simudator/core/module.py
+++ b/src/simudator/core/module.py
@@ -13,8 +13,8 @@ class Module:
     ----------
     signals : dict[str, Signal]
         Dictionary containing all signals connected to the module. Input
-        signals should have keys beginning with `"in_"` and output signals keys
-        beginning with "out_".
+        signals should have keys beginning with 'in\_' and output signals keys
+        beginning with 'out\_'.
     name : str
         Name of the module.
 
@@ -25,7 +25,7 @@ class Module:
     signals : dict[str, Signal]
         The signals connected to this module. The key for a signal can be
         regarded as the name of a signal 'port' of the module. The keys should
-        be prefixed with 'in_' for input signals and 'out_' for output signals.
+        be prefixed with 'in\_' for input signals and 'out\_' for output signals.
     """
 
     def __init__(self, signals: dict[str, Signal], name: str = "") -> None:
@@ -101,7 +101,7 @@ class Module:
     def get_output_signals(self) -> list[Signal]:
         """Return the output signals of the module.
 
-        Assumes all output signals are stored with a key beginning in 'out' in
+        Assumes all output signals are stored with a key beginning in 'out\_' in
         the signals dictionary.
 
         Returns
@@ -114,7 +114,7 @@ class Module:
     def get_input_signals(self) -> list[Signal]:
         """Return the input signals of the module.
 
-        Assumes all input signals are stored with a key beginning in 'in' in
+        Assumes all input signals are stored with a key beginning in 'in\_' in
         the signals dictionary.
 
         Returns
diff --git a/src/simudator/core/modules/demux.py b/src/simudator/core/modules/demux.py
index 3ab7d0e5660065e9b390962bb259460e3213ece4..269138a4bb509972e5c4ef7d4af9f50c9ddc08c7 100644
--- a/src/simudator/core/modules/demux.py
+++ b/src/simudator/core/modules/demux.py
@@ -19,7 +19,7 @@ class Demux(Module):
     bit_length : int
         Maximum number of bits for the value outputted by the demux. All extra
         bits of the input value are discarded.
-    input : Signals
+    input : Signal
         Input signal of which the value is forwarded to the currently
         selected output signal.
     outputs : list[Signal]
diff --git a/src/simudator/core/modules/memory.py b/src/simudator/core/modules/memory.py
index c8c0a7766eb839a4418d9f128688c3e87f802703..d5f42d06adfa1657ef3df4e55809b2fb0960c9cb 100644
--- a/src/simudator/core/modules/memory.py
+++ b/src/simudator/core/modules/memory.py
@@ -5,10 +5,6 @@ from typing import Any
 from simudator.core.module import Module
 from simudator.core.signal import Signal
 
-# Used to pad the values of the memory when saving to file
-MEMORY_VALUE_PADDING = 2
-MEMORY_ADDRESS_PADDING = 2
-
 
 class Memory(Module):
     """
@@ -31,6 +27,13 @@ class Memory(Module):
         Name of the module.
     """
 
+    """
+    Constants used to textually pad the values of the memory when saving to
+    file.
+    """
+    MEMORY_VALUE_PADDING = 2
+    MEMORY_ADDRESS_PADDING = 2
+
     def __init__(
         self,
         input: Signal,
@@ -133,9 +136,9 @@ class Memory(Module):
         file.write(self.name + ":\n")
         for index, value in enumerate(self._memory):
             # Write the address in hex and add ': ' to the end
-            file.write(hex(index)[2:].rjust(MEMORY_ADDRESS_PADDING, "0") + ": ")
+            file.write(hex(index)[2:].rjust(Memory.MEMORY_ADDRESS_PADDING, "0") + ": ")
             # Write the value in hex
-            file.write(hex(value)[2:].rjust(MEMORY_VALUE_PADDING, "0"))
+            file.write(hex(value)[2:].rjust(Memory.MEMORY_VALUE_PADDING, "0"))
             file.write("\n")
 
         file.write("\n")