diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py index 24cad248e7f16469ce0b0db2b8226ef01902be9d..c5a5a2874a790920841be4b698c756ec73f5778e 100644 --- a/src/simudator/core/module.py +++ b/src/simudator/core/module.py @@ -87,7 +87,7 @@ class Module: Returns ------- dict[str, Any] - Parameter of the module represented as a dictionary with one key for + Parameters of the module represented as a dictionary with one key for each parameter variable. """ param_dict = dict() diff --git a/src/simudator/core/modules/mux.py b/src/simudator/core/modules/mux.py index 851b1b9f28cfc599be3a2b4921d620a2f75d9412..bb193b69404f4a86a301f8afcac71be786d363d8 100644 --- a/src/simudator/core/modules/mux.py +++ b/src/simudator/core/modules/mux.py @@ -87,10 +87,10 @@ class Mux(Module): return state def get_parameter(self) -> dict[str, Any]: - paramter = super().get_state() - paramter["bit_length"] = self._bit_length + parameter = super().get_state() + parameter["bit_length"] = self._bit_length - return paramter + return parameter def save_state_to_file(self, file_path: str) -> bool: content = self.name + ":\nvalue: " + str(self._value) + "\n\n" diff --git a/src/simudator/core/modules/register.py b/src/simudator/core/modules/register.py index 1e735b2904174a89d327804073a6c3ea57bafedc..9e6c7b7573ce863adbf0c641d180ca7043beeede 100644 --- a/src/simudator/core/modules/register.py +++ b/src/simudator/core/modules/register.py @@ -115,7 +115,7 @@ class IntegerRegister(Register): name: str | None = None, ) -> None: - # set the registers name + # set the register name if name is None: name = f"{bit_length}-bit register"