Skip to content
GitLab
Explore
Sign in
Computer Engineering
B-ASIC - Better ASIC Toolbox
Merge requests
Open
0
Merged
48
Closed
1
All
49
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Created date
Fix VHDL code imports and some spelling
!374
· created
May 11, 2023
by
Oscar Gustafsson
Code generation
Code quality
Merged
Approved
0
updated
May 11, 2023
Fix typing, spelling errors and minor tests
!397
· created
May 17, 2023
by
Oscar Gustafsson
Code quality
Documentation
Testing
Typing
Merged
Approved
0
updated
May 17, 2023
Minor fixes
!403
· created
May 18, 2023
by
Oscar Gustafsson
Code quality
Documentation
Merged
Approved
0
updated
May 18, 2023
Add numpydoc validation and pyupgrade
!405
· created
May 18, 2023
by
Oscar Gustafsson
Code quality
Documentation
Merged
Approved
0
updated
May 18, 2023
Add port access bar plots
!407
· created
May 18, 2023
by
Oscar Gustafsson
Code quality
Documentation
Enhancement
Graphical representation
Resource allocation
Scheduling GUI
Merged
Approved
0
updated
May 18, 2023
Minor refactoring and cleanup
!411
· created
Jun 02, 2023
by
Oscar Gustafsson
Code quality
Scheduling
Scheduling GUI
Merged
Approved
0
updated
Jun 02, 2023
Change GraphID numbering to be zero-based
!417
· created
Jun 15, 2023
by
Hugo Winbladh
Autumn version
Code quality
Merged
Approved
0
updated
Jun 19, 2023
Pre-commit updates and spell checker
!437
· created
Apr 11, 2024
by
Oscar Gustafsson
Code quality
Merged
Approved
0
updated
Apr 11, 2024
Add __slots__ to some classes
!442
· created
Apr 23, 2024
by
Oscar Gustafsson
Code quality
Merged
Approved
0
updated
Apr 23, 2024
Prev
1
2
3
Next