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  • Computer EngineeringComputer Engineering
  • B-ASIC - Better ASIC ToolboxB-ASIC - Better ASIC Toolbox
  • Issues
  • #95

Handle delays differently in precedence graph generation

Description of issue:

Right now, the predence graph is drawn in a slightly strange way when there are loops. It should improve if the delay elements are duplicated so that the signal comes from one node at the left (without any inputs to the delay element) and goes to a different node (with the same name) when it is computed.

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