diff --git a/b_asic/GUI/arrow.py b/b_asic/GUI/arrow.py
index e62a9cbe936d2f8b4ad5255e87149136693d17a1..66cfaae4dc1e2ae30495320591741c1d72eecc68 100644
--- a/b_asic/GUI/arrow.py
+++ b/b_asic/GUI/arrow.py
@@ -11,6 +11,7 @@ if TYPE_CHECKING:
from b_asic.GUI.drag_button import DragButton
from b_asic.GUI.main_window import SFGMainWindow
from b_asic.GUI.port_button import PortButton
+ from b_asic.operation import Operation
from b_asic.port import InputPort, OutputPort
diff --git a/b_asic/GUI/gui_interface.py b/b_asic/GUI/gui_interface.py
index 9265a48d28e866edd6946182f39da94f297672b3..8c6fe60124e4bf8f58775486eef344dac18947b1 100644
--- a/b_asic/GUI/gui_interface.py
+++ b/b_asic/GUI/gui_interface.py
@@ -1,7 +1,7 @@
# -*- coding: utf-8 -*-
# Originally generated from QT designer, but now manually maintained
-from qtpy import QtCore, QtGui, QtWidgets
+from qtpy import QtCore, QtWidgets
class Ui_main_window(object):
diff --git a/b_asic/codegen/vhdl/__init__.py b/b_asic/codegen/vhdl/__init__.py
index 8ffcf487cffbc93e232bf59d00e5425fef5548e0..5d6625b402076302506d63650de985476f301783 100644
--- a/b_asic/codegen/vhdl/__init__.py
+++ b/b_asic/codegen/vhdl/__init__.py
@@ -18,15 +18,19 @@ def write(
start: Optional[str] = None,
):
"""
- Base VHDL code generation utility. `f'{VHDL_TAB*indent_level}'` is first written to the :class:`io.TextIOWrapper`
- object `f`. Immediatly after the indentation, `text` is written to `f`. Finally, `text` is also written to `f`.
+ Base VHDL code generation utility.
+
+ `f'{VHDL_TAB*indent_level}'` is first written to the :class:`io.TextIOWrapper`
+ object `f`. Immediatly after the indentation, `text` is written to `f`. Finally,
+ `text` is also written to `f`.
Parameters
----------
f : :class:`io.TextIOWrapper`
The file object to emit VHDL code to.
indent_level : int
- Indentation level to use. Exactly ``f'{VHDL_TAB*indent_level}`` is written before the text is written.
+ Indentation level to use. Exactly ``f'{VHDL_TAB*indent_level}`` is written
+ before the text is written.
text : str
The text to write to.
end : str, default: '\n'
@@ -43,7 +47,9 @@ def write_lines(
f: TextIOWrapper, lines: List[Union[Tuple[int, str], Tuple[int, str, str]]]
):
"""
- Multiline VHDL code generation utility. Each tuple (int, str, [int]) in the list `lines` is written to the
+ Multiline VHDL code generation utility.
+
+ Each tuple (int, str, [int]) in the list `lines` is written to the
:class:`io.TextIOWrapper` object `f` using the :function:`vhdl.write` function.
Parameters
@@ -53,8 +59,8 @@ def write_lines(
lines : list of tuple (int,str) [1], or list of tuple (int,str,str) [2]
[1]: The first `int` of the tuple is used as indentation level for the line and
the second `str` of the tuple is the content of the line.
- [2]: Same as [1], but the third `str` of the tuple is passed to parameter `end` when calling
- :function:`vhdl.write`.
+ [2]: Same as [1], but the third `str` of the tuple is passed to parameter `end`
+ when calling :function:`vhdl.write`.
"""
for tpl in lines:
if len(tpl) == 2:
diff --git a/b_asic/codegen/vhdl/architecture.py b/b_asic/codegen/vhdl/architecture.py
index eca28cdc4728a019dfa165e7521d8203bb16e9ca..4f585f702c0d97f115052d0caafabffb7cae4b77 100644
--- a/b_asic/codegen/vhdl/architecture.py
+++ b/b_asic/codegen/vhdl/architecture.py
@@ -22,7 +22,7 @@ def memory_based_storage(
input_sync: bool = True,
):
"""
- Generate the VHDL architecture for a memory based architecture from a process collection of memory variables.
+ Generate the VHDL architecture for a memory-based storage architecture.
Parameters
----------
@@ -44,8 +44,9 @@ def memory_based_storage(
Total concurrent memory accesses possible.
input_sync : bool, default: True
Add registers to the input signals (enable signal and data input signals).
- Adding registers to the inputs allow pipelining of address generation (which is added automatically).
- For large interleavers, this can improve timing significantly.
+ Adding registers to the inputs allow pipelining of address generation (which
+ is added automatically). For large interleavers, this can improve timing
+ significantly.
"""
# Code settings
@@ -230,7 +231,8 @@ def memory_based_storage(
f,
4,
'when'
- f' {(mv.start_time+read_time-int(not(input_sync))) % schedule_time} =>',
+ f' {(mv.start_time+read_time-int(not(input_sync))) % schedule_time}'
+ ' =>',
)
vhdl.write_lines(
f,
diff --git a/b_asic/codegen/vhdl/common.py b/b_asic/codegen/vhdl/common.py
index cece97a2d0cf88ba42859f874092103ca50f520e..941bdaa271bcc4e72b1b5a557c82553418c3889e 100644
--- a/b_asic/codegen/vhdl/common.py
+++ b/b_asic/codegen/vhdl/common.py
@@ -51,7 +51,8 @@ def ieee_header(
numeric_std: bool = True,
):
"""
- Write the standard IEEE VHDL use header with includes of std_logic_1164 and numeric_std.
+ Write the standard IEEE VHDL use header with includes of std_logic_1164 and
+ numeric_std.
Parameters
----------
@@ -97,11 +98,13 @@ def signal_decl(
name_pad : int, optional
An optional left padding value applied to the name.
vivado_ram_style : string, optional
- An optional Xilinx Vivado RAM style attribute to apply to this signal delcaration.
- If set, exactly one of: "block", "distributed", "registers", "ultra", "mixed" or "auto".
+ An optional Xilinx Vivado RAM style attribute to apply to this signal
+ declaration. If set, exactly one of: "block", "distributed", "registers",
+ "ultra", "mixed" or "auto".
quartus_ram_style : string, optional
- An optional Quartus Prime RAM style attribute to apply to this signal delcaration.
- If set, exactly one of: "M4K", "M9K", "M10K", "M20K", "M144K", "MLAB" or "logic".
+ An optional Quartus Prime RAM style attribute to apply to this signal
+ declaration. If set, exactly one of: "M4K", "M9K", "M10K", "M20K", "M144K",
+ "MLAB" or "logic".
"""
# Spacing of VHDL signals declaration always with a single tab
name_pad = name_pad or 0
@@ -182,7 +185,7 @@ def process_prologue(
name: Optional[str] = None,
):
"""
- Write only the prologue of a regular VHDL process with a user provided sensitivity list.
+ Write the prologue of a regular VHDL process with a user provided sensitivity list.
This method should almost always be followed by a :func:`process_epilogue`.
@@ -238,10 +241,12 @@ def synchronous_process_prologue(
name: Optional[str] = None,
):
"""
- Write only the prologue of a regular VHDL synchronous process with a single clock object in the sensitivity list
- triggering a rising edge block by some body of VHDL code.
+ Write the prologue of a regular VHDL synchronous process with a single clock object.
- This method should almost always be followed by a :func:`synchronous_process_epilogue`.
+ The clock is the only item in the sensitivity list and is triggering a rising edge
+ block by some body of VHDL code.
+
+ This method is almost always followed by a :func:`synchronous_process_epilogue`.
Parameters
----------
@@ -265,8 +270,10 @@ def synchronous_process_epilogue(
name: Optional[str] = None,
):
"""
- Write only the epilogue of a regular VHDL synchronous process with a single clock object in the sensitivity list
- triggering a rising edge block by some body of VHDL code.
+ Write only the epilogue of a regular VHDL synchronous process with a single clock.
+
+ The clock is the only item in the sensitivity list and is triggering a rising edge
+ block by some body of VHDL code.
Parameters
----------
@@ -292,8 +299,10 @@ def synchronous_process(
name: Optional[str] = None,
):
"""
- Write a regular VHDL synchronous process with a single clock object in the sensitivity list triggering
- a rising edge block by some body of VHDL code.
+ Write a regular VHDL synchronous process with a single clock.
+
+ The clock is the only item in the sensitivity list and is triggering a rising edge
+ block by some body of VHDL code.
Parameters
----------
diff --git a/b_asic/codegen/vhdl/entity.py b/b_asic/codegen/vhdl/entity.py
index e79f7753f17670fa943b42f0a4725412eee358d2..9673baac6c4a88023b51ca1d97cd70de66dd5902 100644
--- a/b_asic/codegen/vhdl/entity.py
+++ b/b_asic/codegen/vhdl/entity.py
@@ -55,7 +55,9 @@ def memory_based_storage(
# Write the input port specification
f.write(f'{2*VHDL_TAB}-- Memory port I/O\n')
- read_ports: set[Port] = set(sum((mv.read_ports for mv in collection), ())) # type: ignore
+ read_ports: set[Port] = set(
+ sum((mv.read_ports for mv in collection), ())
+ ) # type: ignore
for idx, read_port in enumerate(read_ports):
port_name = read_port if isinstance(read_port, int) else read_port.name
port_name = 'p_' + str(port_name) + '_in'
diff --git a/b_asic/port.py b/b_asic/port.py
index f334122f76ebd0219699eb5c6e469092107ce388..51b0173dc15ebd3e20035350e51b44ce466214c9 100644
--- a/b_asic/port.py
+++ b/b_asic/port.py
@@ -95,7 +95,9 @@ class Port(ABC):
@property
@abstractmethod
def name(self) -> str:
- """Return a name consisting of *graph_id* of the related operation and the port number.
+ """
+ Return a name consisting of *graph_id* of the related operation and the port
+ number.
"""
diff --git a/b_asic/quantization.py b/b_asic/quantization.py
index 6fae9d2722aff3c99c39bfd98ac4efbe355b0a0a..e491bca301d10dddff0be862571d7b7369c62683 100644
--- a/b_asic/quantization.py
+++ b/b_asic/quantization.py
@@ -51,12 +51,13 @@ def quantize(
Quantization happens before overflow, so, e.g., rounding may lead to an overflow.
The total number of bits is *fractional_bits* + *integer_bits*. However, there is
- no check that this will be a positive number. Note that the sign bit is included in these
- bits. If *integer_bits* is not given, then use 1, i.e., the result is between
+ no check that this will be a positive number. Note that the sign bit is included in
+ these bits. If *integer_bits* is not given, then use 1, i.e., the result is between
.. math:: -1 \leq \text{value} \leq 1-2^{-\text{fractional_bits}}
- If *value* is a complex number, the real and imaginary parts are quantized separately.
+ If *value* is a complex number, the real and imaginary parts are quantized
+ separately.
Parameters
----------
diff --git a/b_asic/scheduler_gui/compile.py b/b_asic/scheduler_gui/compile.py
index 88c8f9837ca5c0d6388a7aef384ae4e30704d06c..8095aa4c361cddf6bee7821102e5dcc79b9af3dd 100644
--- a/b_asic/scheduler_gui/compile.py
+++ b/b_asic/scheduler_gui/compile.py
@@ -37,8 +37,8 @@ def _check_filenames(*filenames: str) -> None:
def _check_qt_version() -> None:
"""
- Check if PySide2, PyQt5, PySide6, or PyQt6 is installed, otherwise raise AssertionError
- exception.
+ Check if PySide2, PyQt5, PySide6, or PyQt6 is installed, otherwise raise
+ AssertionError exception.
"""
assert (
uic.PYSIDE2 or uic.PYQT5 or uic.PYSIDE6 or uic.PYQT6
diff --git a/b_asic/types.py b/b_asic/types.py
index 1f37cebb556a05646def9605c043f4ac1f5ee4cb..b141be1c8fc5b61fb70fc41daa2d2124b90696af 100644
--- a/b_asic/types.py
+++ b/b_asic/types.py
@@ -9,8 +9,8 @@ NumRuntime = (complex, float, int)
Name = str
# # We want to be able to initialize Name with String literals, but still have the
# # benefit of static type checking that we don't pass non-names to name locations.
-# # However, until python 3.11 a string literal type was not available. In those versions,
-# # we'll fall back on just aliasing `str` => Name.
+# # However, until python 3.11 a string literal type was not available. In those
+# # versions, we'll fall back on just aliasing `str` => Name.
# if sys.version_info >= (3, 11):
# from typing import LiteralString
# Name: TypeAlias = NewType("Name", str) | LiteralString