From d1af9c2e40b051859fd5a110259122a666c0f107 Mon Sep 17 00:00:00 2001
From: Oscar Gustafsson <oscar.gustafsson@gmail.com>
Date: Tue, 9 May 2023 14:52:28 +0200
Subject: [PATCH] Last code formatting fixes
---
b_asic/codegen/vhdl/common.py | 2 +-
b_asic/gui_utils/plot_window.py | 19 ++++++------------
b_asic/resources.py | 35 ++++++++++++++++++---------------
b_asic/signal_flow_graph.py | 18 +++++++++--------
pyproject.toml | 3 +++
5 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/b_asic/codegen/vhdl/common.py b/b_asic/codegen/vhdl/common.py
index 941bdaa2..5e51e20b 100644
--- a/b_asic/codegen/vhdl/common.py
+++ b/b_asic/codegen/vhdl/common.py
@@ -24,7 +24,7 @@ def b_asic_preamble(f: TextIOWrapper):
try:
process = Popen(['git', 'rev-parse', '--short', 'HEAD'], stdout=PIPE)
git_commit_id = process.communicate()[0].decode('utf-8').strip()
- except:
+ except: # noqa: E722
pass
vhdl.write_lines(
f,
diff --git a/b_asic/gui_utils/plot_window.py b/b_asic/gui_utils/plot_window.py
index c156411e..28602c3f 100644
--- a/b_asic/gui_utils/plot_window.py
+++ b/b_asic/gui_utils/plot_window.py
@@ -11,7 +11,7 @@ from matplotlib.backends.backend_qt5agg import NavigationToolbar2QT as Navigatio
from matplotlib.figure import Figure
from matplotlib.ticker import MaxNLocator
from qtpy.QtCore import Qt
-from qtpy.QtWidgets import ( # QFrame,; QScrollArea,; QLineEdit,; QSizePolicy,; QLabel,; QFileDialog,; QShortcut,
+from qtpy.QtWidgets import (
QApplication,
QCheckBox,
QHBoxLayout,
@@ -35,7 +35,8 @@ class PlotWindow(QWidget):
Parameters
----------
sim_result : dict
- Simulation results of the form obtained from :attr:`~b_asic.simulation.Simulation.results`.
+ Simulation results of the form obtained from
+ :attr:`~b_asic.simulation.Simulation.results`.
sfg_name : str, optional
The name of the SFG.
parent : optional
@@ -161,9 +162,7 @@ class PlotWindow(QWidget):
list_item = QListWidgetItem(key)
listitems[key] = list_item
self._checklist.addItem(list_item)
- list_item.setCheckState(
- Qt.CheckState.Unchecked # CheckState: Qt.CheckState.{Unchecked, PartiallyChecked, Checked}
- )
+ list_item.setCheckState(Qt.CheckState.Unchecked)
for key in initially_checked:
listitems[key].setCheckState(Qt.CheckState.Checked)
# self._checklist.setFixedWidth(150)
@@ -202,13 +201,6 @@ class PlotWindow(QWidget):
self._legend = self._plot_axes.legend()
self._plot_canvas.draw()
- # def _ontop_checkbox_change(self, checkState):
- # Bugg: It seems the window closes if you change the WindowStaysOnTopHint.
- # (Nothing happens if "changing" from False to False or True to True)
- # self.setWindowFlag(Qt.WindowStaysOnTopHint, on = (checkState == Qt.CheckState.Checked))
- # self.setWindowFlag(Qt.WindowStaysOnTopHint, on = True)
- # print("_ontop_checkbox_change")
-
def _button_all_click(self, event):
self._auto_redraw = False
for x in range(self._checklist.count()):
@@ -253,7 +245,8 @@ def start_simulation_dialog(
Parameters
----------
sim_results : dict
- Simulation results of the form obtained from :attr:`~b_asic.simulation.Simulation.results`.
+ Simulation results of the form obtained from
+ :attr:`~b_asic.simulation.Simulation.results`.
sfg_name : str, optional
The name of the SFG.
"""
diff --git a/b_asic/resources.py b/b_asic/resources.py
index 9b2a6bbc..208c0239 100644
--- a/b_asic/resources.py
+++ b/b_asic/resources.py
@@ -58,9 +58,10 @@ def _sanitize_port_option(
Returns
-------
- Returns a triple int tuple (read_ports, write_ports, total_ports) equal to the input, or sanitized if one of the input equals None.
- If total_ports is set to None at the input, it is set to read_ports+write_ports at the output.
- If read_ports or write_ports is set to None at the input, it is set to total_ports at the output.
+ Returns a triple int tuple (read_ports, write_ports, total_ports) equal to the
+ input, or sanitized if one of the input equals None. If total_ports is set to None
+ at the input, it is set to read_ports+write_ports at the output. If read_ports or
+ write_ports is set to None at the input, it is set to total_ports at the output.
"""
if total_ports is None:
@@ -1091,18 +1092,18 @@ class ProcessCollection:
Word length of the memory variable objects.
assignment : set
A possible cell assignment to use when generating the memory based storage.
- The cell assignment is a dictionary int to ProcessCollection where the integer
- corresponds to the cell to assign all MemoryVariables in corresponding process
- collection.
+ The cell assignment is a dictionary int to ProcessCollection where the
+ integer corresponds to the cell to assign all MemoryVariables in
+ corresponding process collection.
If unset, each MemoryVariable will be assigned to a unique single cell.
read_ports : int, default: 1
The number of read ports used when splitting process collection based on
- memory variable access. If total ports in unset, this parameter has to be set
- and total_ports is assumed to be read_ports + write_ports.
+ memory variable access. If total ports in unset, this parameter has to be
+ set and total_ports is assumed to be read_ports + write_ports.
write_ports : int, default: 1
The number of write ports used when splitting process collection based on
- memory variable access. If total ports is unset, this parameter has to be set
- and total_ports is assumed to be read_ports + write_ports.
+ memory variable access. If total ports is unset, this parameter has to be
+ set and total_ports is assumed to be read_ports + write_ports.
total_ports : int, default: 2
The total number of ports used when splitting process collection based on
memory variable access.
@@ -1219,9 +1220,11 @@ class ProcessCollection:
total_ports: int = 2,
):
"""
- Generate VHDL code for register based storages of processes based on Forward-Backward Register Allocation [1].
+ Generate VHDL code for register based storages of processes based on
+ Forward-Backward Register Allocation [1].
- [1]: K. Parhi: VLSI Digital Signal Processing Systems: Design and Implementation, Ch. 6.3.2
+ [1]: K. Parhi: VLSI Digital Signal Processing Systems: Design and
+ Implementation, Ch. 6.3.2
Parameters
----------
@@ -1233,12 +1236,12 @@ class ProcessCollection:
Name used for the VHDL entity.
read_ports : int, default: 1
The number of read ports used when splitting process collection based on
- memory variable access. If total ports in unset, this parameter has to be set
- and total_ports is assumed to be read_ports + write_ports.
+ memory variable access. If total ports in unset, this parameter has to be
+ set and total_ports is assumed to be read_ports + write_ports.
write_ports : int, default: 1
The number of write ports used when splitting process collection based on
- memory variable access. If total ports is unset, this parameter has to be set
- and total_ports is assumed to be read_ports + write_ports.
+ memory variable access. If total ports is unset, this parameter has to be
+ set and total_ports is assumed to be read_ports + write_ports.
total_ports : int, default: 2
The total number of ports used when splitting process collection based on
memory variable access.
diff --git a/b_asic/signal_flow_graph.py b/b_asic/signal_flow_graph.py
index 49884f86..5869e38a 100644
--- a/b_asic/signal_flow_graph.py
+++ b/b_asic/signal_flow_graph.py
@@ -1620,8 +1620,9 @@ class SFG(AbstractOperation):
delay = Delay(name=op.name)
delay.graph_id = op.graph_id
- # Since we're adding a new operation instead of bypassing as in the
- # common case, we also need to hook up the inputs to the delay.
+ # Since we're adding a new operation instead of bypassing as in
+ # the common case, we also need to hook up the inputs to the
+ # delay.
delay.inputs[0].connect(source_op_output)
new_source_op = delay
@@ -1633,7 +1634,8 @@ class SFG(AbstractOperation):
for out_signal in op.outputs[0].signals:
sink_port = out_signal.destination
if sink_port is None:
- # It would be weird if we found a signal that wasn't connected anywhere
+ # It would be weird if we found a signal that wasn't
+ # connected anywhere
raise ValueError("Dangling output port in sfg")
sink_op_idx = id_idx_map[sink_port.operation.graph_id]
@@ -1673,15 +1675,15 @@ class SFG(AbstractOperation):
all_ops = [op for op_list in new_ops for op in op_list]
- # To get the input order correct, we need to know the input order in the original
- # sfg and which operations they correspond to
+ # To get the input order correct, we need to know the input order in the
+ # original sfg and which operations they correspond to
input_ids = [op.graph_id for op in self.input_operations]
output_ids = [op.graph_id for op in self.output_operations]
# Re-order the inputs to the correct order. Internal order of the inputs should
- # be preserved, i.e. for a graph with 2 inputs (in1, in2), in1 must occur before in2,
- # but the "time" order should be reversed. I.e. the input from layer `factor-1` is the
- # first input
+ # be preserved, i.e. for a graph with 2 inputs (in1, in2), in1 must occur before
+ # in2, but the "time" order should be reversed. I.e. the input from layer
+ # `factor-1` is the first input
all_inputs = list(
itertools.chain.from_iterable(
[
diff --git a/pyproject.toml b/pyproject.toml
index a4cf1aa6..141c0faa 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -76,3 +76,6 @@ ignore_missing_imports = true
[tool.coverage.report]
precision = 2
+
+[tool.ruff]
+ignore = ["F403"]
--
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