diff --git a/b_asic/codegen/vhdl/__init__.py b/b_asic/codegen/vhdl/__init__.py
index 168593c177d6d9b7c5d6a92349e08026ac9f2645..8ffcf487cffbc93e232bf59d00e5425fef5548e0 100644
--- a/b_asic/codegen/vhdl/__init__.py
+++ b/b_asic/codegen/vhdl/__init__.py
@@ -63,6 +63,3 @@ def write_lines(
write(f, indent_level=tpl[0], text=tpl[1], end=tpl[2])
else:
raise ValueError('All tuples in list `lines` must have length 2 or 3')
-
-
-from b_asic.codegen.vhdl import architecture, common, entity
diff --git a/b_asic/codegen/vhdl/architecture.py b/b_asic/codegen/vhdl/architecture.py
index 9494828546cb7952f539bc813e990b1d4c6f5807..d41d76f210e575396687ebfb020889e91707429b 100644
--- a/b_asic/codegen/vhdl/architecture.py
+++ b/b_asic/codegen/vhdl/architecture.py
@@ -2,17 +2,18 @@
Module for code generation of VHDL architectures.
"""
from io import TextIOWrapper
-from typing import Dict, List, Set, Tuple, cast
+from typing import TYPE_CHECKING, Dict, Set, Tuple, cast
from b_asic.codegen import vhdl
-from b_asic.codegen.vhdl import VHDL_TAB
from b_asic.process import MemoryVariable, PlainMemoryVariable
-from b_asic.resources import ProcessCollection, _ForwardBackwardTable
+
+if TYPE_CHECKING:
+ from b_asic.resources import ProcessCollection, _ForwardBackwardTable
def write_memory_based_storage(
f: TextIOWrapper,
- assignment: Set[ProcessCollection],
+ assignment: Set["ProcessCollection"],
entity_name: str,
word_length: int,
read_ports: int,
@@ -91,7 +92,7 @@ def write_memory_based_storage(
vhdl.common.write_signal_decl(f, f'write_en_{i}', 'std_logic', name_pad=14)
# Schedule time counter
- vhdl.write(f, 1, f'-- Schedule counter', start='\n')
+ vhdl.write(f, 1, '-- Schedule counter', start='\n')
vhdl.common.write_signal_decl(
f,
name='schedule_cnt',
@@ -101,7 +102,7 @@ def write_memory_based_storage(
# Input sync signals
if input_sync:
- vhdl.write(f, 1, f'-- Input synchronization', start='\n')
+ vhdl.write(f, 1, '-- Input synchronization', start='\n')
for i in range(read_ports):
vhdl.common.write_signal_decl(
f, f'p_{i}_in_sync', 'std_logic_vector(WL-1 downto 0)', name_pad=14
@@ -110,8 +111,8 @@ def write_memory_based_storage(
#
# Architecture body begin
#
- vhdl.write(f, 0, f'begin', start='\n', end='\n\n')
- vhdl.write(f, 1, f'-- Schedule counter')
+ vhdl.write(f, 0, 'begin', start='\n', end='\n\n')
+ vhdl.write(f, 1, '-- Schedule counter')
vhdl.common.write_synchronous_process_prologue(
f=f,
name='schedule_cnt_proc',
@@ -120,17 +121,17 @@ def write_memory_based_storage(
vhdl.write_lines(
f,
[
- (3, f'if rst = \'1\' then'),
- (4, f'schedule_cnt <= 0;'),
- (3, f'else'),
- (4, f'if en = \'1\' then'),
+ (3, 'if rst = \'1\' then'),
+ (4, 'schedule_cnt <= 0;'),
+ (3, 'else'),
+ (4, 'if en = \'1\' then'),
(5, f'if schedule_cnt = {schedule_time-1} then'),
- (6, f'schedule_cnt <= 0;'),
- (5, f'else'),
- (6, f'schedule_cnt <= schedule_cnt + 1;'),
- (5, f'end if;'),
- (4, f'end if;'),
- (3, f'end if;'),
+ (6, 'schedule_cnt <= 0;'),
+ (5, 'else'),
+ (6, 'schedule_cnt <= schedule_cnt + 1;'),
+ (5, 'end if;'),
+ (4, 'end if;'),
+ (3, 'end if;'),
],
)
vhdl.common.write_synchronous_process_epilogue(
@@ -140,7 +141,7 @@ def write_memory_based_storage(
)
if input_sync:
- vhdl.write(f, 1, f'-- Input synchronization', start='\n')
+ vhdl.write(f, 1, '-- Input synchronization', start='\n')
vhdl.common.write_synchronous_process_prologue(
f=f,
name='input_sync_proc',
@@ -155,7 +156,7 @@ def write_memory_based_storage(
)
# Infer memory
- vhdl.write(f, 1, f'-- Memory', start='\n')
+ vhdl.write(f, 1, '-- Memory', start='\n')
vhdl.common.write_asynchronous_read_memory(
f=f,
clk='clk',
@@ -171,7 +172,7 @@ def write_memory_based_storage(
)
# Write address generation
- vhdl.write(f, 1, f'-- Memory write address generation', start='\n')
+ vhdl.write(f, 1, '-- Memory write address generation', start='\n')
if input_sync:
vhdl.common.write_synchronous_process_prologue(
f, clk="clk", name="mem_write_address_proc"
@@ -180,7 +181,7 @@ def write_memory_based_storage(
vhdl.common.write_process_prologue(
f, sensitivity_list="schedule_cnt", name="mem_write_address_proc"
)
- vhdl.write(f, 3, f'case schedule_cnt is')
+ vhdl.write(f, 3, 'case schedule_cnt is')
for i, collection in enumerate(assignment):
for mv in collection:
mv = cast(MemoryVariable, mv)
@@ -191,7 +192,7 @@ def write_memory_based_storage(
(4, f'-- {mv!r}'),
(4, f'when {(mv.start_time) % schedule_time} =>'),
(5, f'write_adr_0 <= {i};'),
- (5, f'write_en_0 <= \'1\';'),
+ (5, 'write_en_0 <= \'1\';'),
],
)
vhdl.write_lines(
@@ -213,11 +214,11 @@ def write_memory_based_storage(
)
# Read address generation
- vhdl.write(f, 1, f'-- Memory read address generation', start='\n')
+ vhdl.write(f, 1, '-- Memory read address generation', start='\n')
vhdl.common.write_synchronous_process_prologue(
f, clk="clk", name="mem_read_address_proc"
)
- vhdl.write(f, 3, f'case schedule_cnt is')
+ vhdl.write(f, 3, 'case schedule_cnt is')
for i, collection in enumerate(assignment):
for mv in collection:
mv = cast(PlainMemoryVariable, mv)
@@ -233,27 +234,27 @@ def write_memory_based_storage(
f,
[
(5, f'read_adr_0 <= {i};'),
- (5, f'read_en_0 <= \'1\';'),
+ (5, 'read_en_0 <= \'1\';'),
],
)
vhdl.write_lines(
f,
[
- (4, f'when others =>'),
- (5, f'read_adr_0 <= 0;'),
- (5, f'read_en_0 <= \'0\';'),
- (3, f'end case;'),
+ (4, 'when others =>'),
+ (5, 'read_adr_0 <= 0;'),
+ (5, 'read_en_0 <= \'0\';'),
+ (3, 'end case;'),
],
)
vhdl.common.write_synchronous_process_epilogue(
f, clk="clk", name="mem_read_address_proc"
)
- vhdl.write(f, 1, f'-- Input and output assignmentn', start='\n')
+ vhdl.write(f, 1, '-- Input and output assignmentn', start='\n')
if input_sync:
- vhdl.write(f, 1, f'write_port_0 <= p_0_in_sync;')
+ vhdl.write(f, 1, 'write_port_0 <= p_0_in_sync;')
else:
- vhdl.write(f, 1, f'write_port_0 <= p_0_in;')
+ vhdl.write(f, 1, 'write_port_0 <= p_0_in;')
p_zero_exec = filter(
lambda p: p.execution_time == 0, (p for pc in assignment for p in pc)
)
@@ -262,7 +263,7 @@ def write_memory_based_storage(
clk='clk',
name='output_reg_proc',
)
- vhdl.write(f, 3, f'case schedule_cnt is')
+ vhdl.write(f, 3, 'case schedule_cnt is')
for p in p_zero_exec:
if input_sync:
write_time = (p.start_time + 1) % schedule_time
@@ -273,8 +274,8 @@ def write_memory_based_storage(
vhdl.write_lines(
f,
[
- (4, f'when others => p_0_out <= read_port_0;'),
- (3, f'end case;'),
+ (4, 'when others => p_0_out <= read_port_0;'),
+ (3, 'end case;'),
],
)
vhdl.common.write_synchronous_process_epilogue(
@@ -287,7 +288,7 @@ def write_memory_based_storage(
def write_register_based_storage(
f: TextIOWrapper,
- forward_backward_table: _ForwardBackwardTable,
+ forward_backward_table: "_ForwardBackwardTable",
entity_name: str,
word_length: int,
read_ports: int,
@@ -330,7 +331,7 @@ def write_register_based_storage(
)
# Schedule time counter
- vhdl.write(f, 1, f'-- Schedule counter')
+ vhdl.write(f, 1, '-- Schedule counter')
vhdl.common.write_signal_decl(
f,
name='schedule_cnt',
@@ -340,7 +341,7 @@ def write_register_based_storage(
)
# Shift register
- vhdl.write(f, 1, f'-- Shift register', start='\n')
+ vhdl.write(f, 1, '-- Shift register', start='\n')
vhdl.common.write_type_decl(
f,
name='shift_reg_type',
@@ -354,7 +355,7 @@ def write_register_based_storage(
)
# Back edge mux decoder
- vhdl.write(f, 1, f'-- Back-edge mux select signal', start='\n')
+ vhdl.write(f, 1, '-- Back-edge mux select signal', start='\n')
vhdl.common.write_signal_decl(
f,
name='back_edge_mux_sel',
@@ -363,7 +364,7 @@ def write_register_based_storage(
)
# Output mux selector
- vhdl.write(f, 1, f'-- Output mux select signal', start='\n')
+ vhdl.write(f, 1, '-- Output mux select signal', start='\n')
vhdl.common.write_signal_decl(
f,
name='out_mux_sel',
@@ -374,8 +375,8 @@ def write_register_based_storage(
#
# Architecture body begin
#
- vhdl.write(f, 0, f'begin', start='\n', end='\n\n')
- vhdl.write(f, 1, f'-- Schedule counter')
+ vhdl.write(f, 0, 'begin', start='\n', end='\n\n')
+ vhdl.write(f, 1, '-- Schedule counter')
vhdl.common.write_synchronous_process_prologue(
f=f,
name='schedule_cnt_proc',
@@ -384,13 +385,13 @@ def write_register_based_storage(
vhdl.write_lines(
f,
[
- (4, f'if en = \'1\' then'),
+ (4, 'if en = \'1\' then'),
(5, f'if schedule_cnt = {schedule_time}-1 then'),
- (6, f'schedule_cnt <= 0;'),
- (5, f'else'),
- (6, f'schedule_cnt <= schedule_cnt + 1;'),
- (5, f'end if;'),
- (4, f'end if;'),
+ (6, 'schedule_cnt <= 0;'),
+ (5, 'else'),
+ (6, 'schedule_cnt <= schedule_cnt + 1;'),
+ (5, 'end if;'),
+ (4, 'end if;'),
],
)
vhdl.common.write_synchronous_process_epilogue(
@@ -400,13 +401,13 @@ def write_register_based_storage(
)
# Shift register back-edge decoding
- vhdl.write(f, 1, f'-- Shift register back-edge decoding', start='\n')
+ vhdl.write(f, 1, '-- Shift register back-edge decoding', start='\n')
vhdl.common.write_synchronous_process_prologue(
f,
clk='clk',
name='shift_reg_back_edge_decode_proc',
)
- vhdl.write(f, 3, f'case schedule_cnt is')
+ vhdl.write(f, 3, 'case schedule_cnt is')
for time, entry in enumerate(forward_backward_table):
if entry.back_edge_to:
assert len(entry.back_edge_to) == 1
@@ -423,9 +424,9 @@ def write_register_based_storage(
vhdl.write_lines(
f,
[
- (4, f'when others =>'),
- (5, f'back_edge_mux_sel <= 0;'),
- (3, f'end case;'),
+ (4, 'when others =>'),
+ (5, 'back_edge_mux_sel <= 0;'),
+ (3, 'end case;'),
],
)
vhdl.common.write_synchronous_process_epilogue(
@@ -435,28 +436,28 @@ def write_register_based_storage(
)
# Shift register multiplexer logic
- vhdl.write(f, 1, f'-- Multiplexers for shift register', start='\n')
+ vhdl.write(f, 1, '-- Multiplexers for shift register', start='\n')
vhdl.common.write_synchronous_process_prologue(
f,
clk='clk',
name='shift_reg_proc',
)
if sync_rst:
- vhdl.write(f, 3, f'if rst = \'1\' then')
+ vhdl.write(f, 3, 'if rst = \'1\' then')
for reg_idx in range(reg_cnt):
vhdl.write(f, 4, f'shift_reg({reg_idx}) <= (others => \'0\');')
- vhdl.write(f, 3, f'else')
+ vhdl.write(f, 3, 'else')
vhdl.write_lines(
f,
[
- (3, f'-- Default case'),
- (3, f'shift_reg(0) <= p_0_in;'),
+ (3, '-- Default case'),
+ (3, 'shift_reg(0) <= p_0_in;'),
],
)
for reg_idx in range(1, reg_cnt):
vhdl.write(f, 3, f'shift_reg({reg_idx}) <= shift_reg({reg_idx-1});')
- vhdl.write(f, 3, f'case back_edge_mux_sel is')
+ vhdl.write(f, 3, 'case back_edge_mux_sel is')
for edge, mux_sel in back_edge_table.items():
vhdl.write_lines(
f,
@@ -468,13 +469,13 @@ def write_register_based_storage(
vhdl.write_lines(
f,
[
- (4, f'when others => null;'),
- (3, f'end case;'),
+ (4, 'when others => null;'),
+ (3, 'end case;'),
],
)
if sync_rst:
- vhdl.write(f, 3, f'end if;')
+ vhdl.write(f, 3, 'end if;')
vhdl.common.write_synchronous_process_epilogue(
f,
@@ -483,36 +484,36 @@ def write_register_based_storage(
)
# Output multiplexer decoding logic
- vhdl.write(f, 1, f'-- Output muliplexer decoding logic', start='\n')
+ vhdl.write(f, 1, '-- Output muliplexer decoding logic', start='\n')
vhdl.common.write_synchronous_process_prologue(
f, clk='clk', name='out_mux_decode_proc'
)
- vhdl.write(f, 3, f'case schedule_cnt is')
+ vhdl.write(f, 3, 'case schedule_cnt is')
for i, entry in enumerate(forward_backward_table):
if entry.outputs_from is not None:
sel = output_mux_table[entry.outputs_from]
vhdl.write(f, 4, f'when {(i-1)%schedule_time} =>')
vhdl.write(f, 5, f'out_mux_sel <= {sel};')
- vhdl.write(f, 3, f'end case;')
+ vhdl.write(f, 3, 'end case;')
vhdl.common.write_synchronous_process_epilogue(
f, clk='clk', name='out_mux_decode_proc'
)
# Output multiplexer logic
- vhdl.write(f, 1, f'-- Output muliplexer', start='\n')
+ vhdl.write(f, 1, '-- Output muliplexer', start='\n')
vhdl.common.write_synchronous_process_prologue(
f,
clk='clk',
name='out_mux_proc',
)
- vhdl.write(f, 3, f'case out_mux_sel is')
+ vhdl.write(f, 3, 'case out_mux_sel is')
for reg_i, mux_i in output_mux_table.items():
vhdl.write(f, 4, f'when {mux_i} =>')
if reg_i < 0:
vhdl.write(f, 5, f'p_0_out <= p_{-1-reg_i}_in;')
else:
vhdl.write(f, 5, f'p_0_out <= shift_reg({reg_i});')
- vhdl.write(f, 3, f'end case;')
+ vhdl.write(f, 3, 'end case;')
vhdl.common.write_synchronous_process_epilogue(
f,
clk='clk',
diff --git a/b_asic/codegen/vhdl/common.py b/b_asic/codegen/vhdl/common.py
index 7925b6f3d4afd669da96d5ae84e6672cd5d458ba..cf3dfee844184cef54148e0180b21716a46a5989 100644
--- a/b_asic/codegen/vhdl/common.py
+++ b/b_asic/codegen/vhdl/common.py
@@ -29,8 +29,8 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):
vhdl.write_lines(
f,
[
- (0, f'--'),
- (0, f'-- This code was automatically generated by the B-ASIC toolbox.'),
+ (0, '--'),
+ (0, '-- This code was automatically generated by the B-ASIC toolbox.'),
(0, f'-- Code generation timestamp: ({datetime.now()})'),
],
)
@@ -39,8 +39,8 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):
vhdl.write_lines(
f,
[
- (0, f'-- URL: https://gitlab.liu.se/da/B-ASIC'),
- (0, f'--', '\n\n'),
+ (0, '-- URL: https://gitlab.liu.se/da/B-ASIC'),
+ (0, '--', '\n\n'),
],
)
@@ -113,7 +113,7 @@ def write_signal_decl(
vhdl.write_lines(
f,
[
- (1, f'attribute ram_style : string;'),
+ (1, 'attribute ram_style : string;'),
(1, f'attribute ram_style of {name} : signal is "{vivado_ram_style}";'),
],
)
@@ -121,7 +121,7 @@ def write_signal_decl(
vhdl.write_lines(
f,
[
- (1, f'attribute ramstyle : string;'),
+ (1, 'attribute ramstyle : string;'),
(1, f'attribute ramstyle of {name} : signal is "{quartus_ram_style}";'),
],
)
@@ -200,7 +200,7 @@ def write_process_prologue(
vhdl.write(f, indent, f'{name}: process({sensitivity_list})')
else:
vhdl.write(f, indent, f'process({sensitivity_list})')
- vhdl.write(f, indent, f'begin')
+ vhdl.write(f, indent, 'begin')
def write_process_epilogue(
@@ -224,7 +224,7 @@ def write_process_epilogue(
An optional name of the ending process.
"""
_ = sensitivity_list
- vhdl.write(f, indent, f'end process', end="")
+ vhdl.write(f, indent, 'end process', end="")
if name is not None:
vhdl.write(f, 0, ' ' + name, end="")
vhdl.write(f, 0, ';')
@@ -253,7 +253,7 @@ def write_synchronous_process_prologue(
An optional name for the process.
"""
write_process_prologue(f, sensitivity_list=clk, indent=indent, name=name)
- vhdl.write(f, indent + 1, f'if rising_edge(clk) then')
+ vhdl.write(f, indent + 1, 'if rising_edge(clk) then')
def write_synchronous_process_epilogue(
@@ -279,7 +279,7 @@ def write_synchronous_process_epilogue(
An optional name for the process
"""
_ = clk
- vhdl.write(f, indent + 1, f'end if;')
+ vhdl.write(f, indent + 1, 'end if;')
write_process_epilogue(f, sensitivity_list=clk, indent=indent, name=name)
@@ -346,7 +346,7 @@ def write_synchronous_memory(
[
(3, f'if {re} = \'1\' then'),
(4, f'{read_name} <= memory({address});'),
- (3, f'end if;'),
+ (3, 'end if;'),
],
)
for write_name, address, we in write_ports:
@@ -355,7 +355,7 @@ def write_synchronous_memory(
[
(3, f'if {we} = \'1\' then'),
(4, f'memory({address}) <= {write_name};'),
- (3, f'end if;'),
+ (3, 'end if;'),
],
)
write_synchronous_process_epilogue(f, clk=clk, name=name)
@@ -393,7 +393,7 @@ def write_asynchronous_read_memory(
[
(3, f'if {we} = \'1\' then'),
(4, f'memory({address}) <= {write_name};'),
- (3, f'end if;'),
+ (3, 'end if;'),
],
)
write_synchronous_process_epilogue(f, clk=clk, name=name)
diff --git a/b_asic/codegen/vhdl/entity.py b/b_asic/codegen/vhdl/entity.py
index 1e0cba8fa13898ecb9fef2aadc98f1d2a69273d5..962ce7bd88774cdf5dc0aaef59671e11f8bdf6c5 100644
--- a/b_asic/codegen/vhdl/entity.py
+++ b/b_asic/codegen/vhdl/entity.py
@@ -33,11 +33,11 @@ def write_memory_based_storage(
f,
[
(0, f'entity {entity_name} is'),
- (1, f'generic('),
- (2, f'-- Data word length'),
+ (1, 'generic('),
+ (2, '-- Data word length'),
(2, f'WL : integer := {word_length}'),
- (1, f');'),
- (1, f'port('),
+ (1, ');'),
+ (1, 'port('),
],
)
@@ -45,11 +45,11 @@ def write_memory_based_storage(
vhdl.write_lines(
f,
[
- (0, f'-- Clock, synchronous reset and enable signals'),
- (2, f'clk : in std_logic;'),
- (2, f'rst : in std_logic;'),
- (2, f'en : in std_logic;'),
- (0, f''),
+ (0, '-- Clock, synchronous reset and enable signals'),
+ (2, 'clk : in std_logic;'),
+ (2, 'rst : in std_logic;'),
+ (2, 'en : in std_logic;'),
+ (0, ''),
],
)
diff --git a/b_asic/gui_utils/about_window.py b/b_asic/gui_utils/about_window.py
index ac7b4cae83df3906a23c945c79b0bab236f5385d..7c203d4fa1bc9a38576df84c5a1046b3d7ce4846 100644
--- a/b_asic/gui_utils/about_window.py
+++ b/b_asic/gui_utils/about_window.py
@@ -32,7 +32,9 @@ class AboutWindow(QDialog):
self._add_information_to_layout()
def _hover_text(self, url):
- # self.setWindowTitle(url) # When removing mouse, the title gets "B-ASIC Scheduler". Where does THAT come from?
+ # self.setWindowTitle(url)
+ # When removing mouse, the title gets "B-ASIC Scheduler".
+ # Where does THAT come from?
if url:
QToolTip.showText(QCursor.pos(), url)
else:
@@ -54,7 +56,8 @@ class AboutWindow(QDialog):
" Computer Engineering</a> at <a"
" href=\"https://liu.se/?l=en\">Linköping University</a>,"
" Sweden.\n\nB-ASIC is released under the <a"
- " href=\"https://gitlab.liu.se/da/B-ASIC/-/blob/master/LICENSE\">MIT-license</a>"
+ " href=\"https://gitlab.liu.se/da/B-ASIC/-/blob/master/LICENSE\">"
+ "MIT-license</a>"
" and any extension to the program should follow that same"
f" license.\n\n*Version: {__version__}*\n\nCopyright 2020-2023,"
" Oscar Gustafsson et al."
@@ -74,9 +77,11 @@ class AboutWindow(QDialog):
self.logo2.setFixedWidth(100)
label3 = QLabel(
- """Additional resources: <a href="https://da.gitlab-pages.liu.se/B-ASIC/">documentation</a>,"""
- """ <a href="https://gitlab.liu.se/da/B-ASIC/">git repository</a>,"""
- """ <a href="https://gitlab.liu.se/da/B-ASIC/-/issues">report issues and suggestions</a>."""
+ 'Additional resources: <a href="https://da.gitlab-pages.liu.se/B-ASIC/">'
+ 'documentation</a>,'
+ ' <a href="https://gitlab.liu.se/da/B-ASIC/">git repository</a>,'
+ ' <a href="https://gitlab.liu.se/da/B-ASIC/-/issues">report issues and'
+ ' suggestions</a>.'
)
label3.setOpenExternalLinks(True)
label3.linkHovered.connect(self._hover_text)
diff --git a/b_asic/gui_utils/plot_window.py b/b_asic/gui_utils/plot_window.py
index c92c8b5af89c5b6e75e42696d41030a3b45158be..cdf565922a9d9cc885f23797a9468d84ef31d1e0 100644
--- a/b_asic/gui_utils/plot_window.py
+++ b/b_asic/gui_utils/plot_window.py
@@ -211,7 +211,7 @@ def start_simulation_dialog(
sfg_name : str, optional
The name of the SFG.
"""
- app = QApplication(sys.argv)
+ QApplication(sys.argv)
win = PlotWindow(sim_result=sim_results, sfg_name=sfg_name)
win.exec_()
diff --git a/b_asic/operation.py b/b_asic/operation.py
index 96f424f62bf2c325afb1cf869300875762163348..4af199a4a472d2ff4e2172e9b550845f19e792da 100644
--- a/b_asic/operation.py
+++ b/b_asic/operation.py
@@ -951,7 +951,7 @@ class AbstractOperation(Operation, AbstractGraphComponent):
for i, input_port in enumerate(self.inputs):
value = input_values[i]
if bits_override is None and input_port.signal_count >= 1:
- bits = input_port.signals[0].bits
+ input_port.signals[0].bits
if bits_override is not None:
if isinstance(value, complex):
raise TypeError(
@@ -992,7 +992,8 @@ class AbstractOperation(Operation, AbstractGraphComponent):
return latency_offsets
def _check_all_latencies_set(self) -> None:
- """Raises an exception if an input or output does not have its latency offset set
+ """
+ Raises an exception if an input or output does not have a latency offset.
"""
self.input_latency_offsets()
self.output_latency_offsets()
@@ -1001,10 +1002,10 @@ class AbstractOperation(Operation, AbstractGraphComponent):
latency_offsets = [i.latency_offset for i in self.inputs]
if any(val is None for val in latency_offsets):
- raise ValueError(
- "Missing latencies for input(s)"
- f" {[i for (i, latency) in enumerate(latency_offsets) if latency is None]}"
- )
+ missing = [
+ i for (i, latency) in enumerate(latency_offsets) if latency is None
+ ]
+ raise ValueError(f"Missing latencies for input(s) {missing}")
return cast(List[int], latency_offsets)
@@ -1012,10 +1013,10 @@ class AbstractOperation(Operation, AbstractGraphComponent):
latency_offsets = [i.latency_offset for i in self.outputs]
if any(val is None for val in latency_offsets):
- raise ValueError(
- "Missing latencies for output(s)"
- f" {[i for (i, latency) in enumerate(latency_offsets) if latency is None]}"
- )
+ missing = [
+ i for (i, latency) in enumerate(latency_offsets) if latency is None
+ ]
+ raise ValueError(f"Missing latencies for output(s) {missing}")
return cast(List[int], latency_offsets)
diff --git a/b_asic/research/__init__.py b/b_asic/research/__init__.py
index 5004affd515dc2a8ee42bb0153bbdafc5141603b..39255ea1b97a81798006ab4154edef681116843c 100644
--- a/b_asic/research/__init__.py
+++ b/b_asic/research/__init__.py
@@ -8,5 +8,6 @@ that they may be useful for someone else as well.
The following module is currently available:
-- :mod:`b_asic.research.interleaver`: generate matrix transposers and random interleavers.
+- :mod:`b_asic.research.interleaver`: generate matrix transposers and random
+ interleavers.
"""
diff --git a/b_asic/resources.py b/b_asic/resources.py
index 2f582e3fe950ce147c0790fa22b4e345ea86c505..3fd5b37748a790ebeea7cdd364cd81657f0f0b21 100644
--- a/b_asic/resources.py
+++ b/b_asic/resources.py
@@ -311,7 +311,7 @@ class _ForwardBackwardTable:
# All passes failed, raise exception...
raise ValueError(
- f"Can't backward allocate any variable. This should not happen."
+ "Can't backward allocate any variable. This should not happen."
)
def __getitem__(self, key):
@@ -325,7 +325,9 @@ class _ForwardBackwardTable:
def __str__(self):
# Text width of input and output column
- lst_w = lambda proc_lst: reduce(lambda n, p: n + len(str(p)) + 1, proc_lst, 0)
+ def lst_w(proc_lst):
+ return reduce(lambda n, p: n + len(str(p)) + 1, proc_lst, 0)
+
input_col_w = max(5, max(lst_w(pl.inputs) for pl in self.table) + 1)
output_col_w = max(5, max(lst_w(pl.outputs) for pl in self.table) + 1)
@@ -499,7 +501,7 @@ class ProcessCollection:
# Generate the life-time chart
for i, process in enumerate(_sorted_nicely(self._collection)):
- bar_row = i if row == None else row
+ bar_row = i if row is None else row
bar_start = process.start_time % self._schedule_time
bar_end = process.start_time + process.execution_time
bar_end = (
@@ -553,7 +555,7 @@ class ProcessCollection:
_ax.xaxis.set_major_locator(MaxNLocator(integer=True)) # type: ignore
_ax.yaxis.set_major_locator(MaxNLocator(integer=True)) # type: ignore
_ax.set_xlim(0, self._schedule_time) # type: ignore
- if row == None:
+ if row is None:
_ax.set_ylim(0.25, len(self._collection) + 0.75) # type: ignore
else:
pass
@@ -998,11 +1000,16 @@ class ProcessCollection:
# Make sure that concurrent reads/writes do not surpass the port setting
for mv in self:
- filter_write = lambda p: p.start_time == mv.start_time
- filter_read = (
- lambda p: (p.start_time + p.execution_time) % self._schedule_time
- == mv.start_time + mv.execution_time % self._schedule_time
- )
+
+ def filter_write(p):
+ return p.start_time == mv.start_time
+
+ def filter_read(p):
+ return (
+ (p.start_time + p.execution_time) % self._schedule_time
+ == mv.start_time + mv.execution_time % self._schedule_time
+ )
+
needed_write_ports = len(list(filter(filter_write, self)))
needed_read_ports = len(list(filter(filter_read, self)))
if needed_write_ports > write_ports + 1:
@@ -1017,14 +1024,14 @@ class ProcessCollection:
)
with open(filename, 'w') as f:
- from b_asic.codegen import vhdl
+ from b_asic.codegen.vhdl import architecture, common, entity
- vhdl.common.write_b_asic_vhdl_preamble(f)
- vhdl.common.write_ieee_header(f)
- vhdl.entity.write_memory_based_storage(
+ common.write_b_asic_vhdl_preamble(f)
+ common.write_ieee_header(f)
+ entity.write_memory_based_storage(
f, entity_name=entity_name, collection=self, word_length=word_length
)
- vhdl.architecture.write_memory_based_storage(
+ architecture.write_memory_based_storage(
f,
assignment=assignment,
entity_name=entity_name,
diff --git a/b_asic/simulation.py b/b_asic/simulation.py
index 1defde586c2cc8d32d80f3a7719b69ee822e93f6..7e449eef7daef19c20b4fc7ae4bcf06d27b53c7b 100644
--- a/b_asic/simulation.py
+++ b/b_asic/simulation.py
@@ -204,7 +204,8 @@ class Simulation:
appropriate output index.
Example result after 3 iterations::
- {"c1": [3, 6, 7], "c2": [4, 5, 5], "bfly1.0": [7, 0, 0], "bfly1.1": [-1, 0, 2], "0": [7, -2, -1]}
+ {"c1": [3, 6, 7], "c2": [4, 5, 5], "bfly1.0": [7, 0, 0], "bfly1.1":\
+ [-1, 0, 2], "0": [7, -2, -1]}
"""
return {key: np.array(value) for key, value in self._results.items()}
diff --git a/test/fixtures/operation_tree.py b/test/fixtures/operation_tree.py
index 8b2ae8c36fc7383237c35ae6fbf5e3318cd361d6..0213466801404454c27fb38369d172fa3863358c 100644
--- a/test/fixtures/operation_tree.py
+++ b/test/fixtures/operation_tree.py
@@ -1,6 +1,6 @@
import pytest
-from b_asic import Addition, Butterfly, Constant, Signal
+from b_asic import Addition, Butterfly, Constant
@pytest.fixture
diff --git a/test/fixtures/schedule.py b/test/fixtures/schedule.py
index 15bb0038ec48a219cf465dc64f67ab626769afd9..c5a78609776642dd6db4cc3b425897a07160b770 100644
--- a/test/fixtures/schedule.py
+++ b/test/fixtures/schedule.py
@@ -1,5 +1,3 @@
-from test.fixtures.signal_flow_graph import precedence_sfg_delays
-
import pytest
from b_asic.core_operations import Addition, ConstantMultiplication
@@ -9,9 +7,7 @@ from b_asic.schedule import Schedule
@pytest.fixture
def secondorder_iir_schedule(precedence_sfg_delays):
precedence_sfg_delays.set_latency_of_type(Addition.type_name(), 4)
- precedence_sfg_delays.set_latency_of_type(
- ConstantMultiplication.type_name(), 3
- )
+ precedence_sfg_delays.set_latency_of_type(ConstantMultiplication.type_name(), 3)
schedule = Schedule(precedence_sfg_delays, scheduling_algorithm="ASAP")
return schedule
diff --git a/test/test_process.py b/test/test_process.py
index 0a1f19bc6cb6e6fe27bc5831356203908836435e..ea53284889ee43bdbcfd75fc313a3d7a50c1297e 100644
--- a/test/test_process.py
+++ b/test/test_process.py
@@ -1,7 +1,5 @@
import re
-import pytest
-
from b_asic.process import PlainMemoryVariable
diff --git a/test/test_resources.py b/test/test_resources.py
index ea17a0b520e31b7dc8288c6296893f124d421038..5b1a484e82d2d461261d5529fc0148a1818ca143 100644
--- a/test/test_resources.py
+++ b/test/test_resources.py
@@ -3,12 +3,11 @@ import pickle
import matplotlib.pyplot as plt
import pytest
-from b_asic.process import PlainMemoryVariable
from b_asic.research.interleaver import (
generate_matrix_transposer,
generate_random_interleaver,
)
-from b_asic.resources import ProcessCollection, draw_exclusion_graph_coloring
+from b_asic.resources import ProcessCollection
class TestProcessCollectionPlainMemoryVariable:
@@ -73,14 +72,14 @@ class TestProcessCollectionPlainMemoryVariable:
collection = generate_matrix_transposer(rows=4, cols=8, min_lifetime=2)
assignment = collection.graph_color_cell_assignment()
collection.generate_memory_based_storage_vhdl(
- filename=f'b_asic/codegen/testbench/streaming_matrix_transposition_memory_4x8.vhdl',
- entity_name=f'streaming_matrix_transposition_memory_4x8',
+ filename='b_asic/codegen/testbench/streaming_matrix_transposition_memory_4x8.vhdl',
+ entity_name='streaming_matrix_transposition_memory_4x8',
assignment=assignment,
word_length=16,
)
collection.generate_register_based_storage_vhdl(
- filename=f'b_asic/codegen/testbench/streaming_matrix_transposition_register_4x8.vhdl',
- entity_name=f'streaming_matrix_transposition_register_4x8',
+ filename='b_asic/codegen/testbench/streaming_matrix_transposition_register_4x8.vhdl',
+ entity_name='streaming_matrix_transposition_register_4x8',
word_length=16,
)
diff --git a/test/test_sfg.py b/test/test_sfg.py
index a84a280d0037cccb92386418b6f524f820647bff..ce95b1060b7c1a614d4296b4a722616565b547ca 100644
--- a/test/test_sfg.py
+++ b/test/test_sfg.py
@@ -1398,7 +1398,7 @@ class TestSFGErrors:
in2 = Input()
adaptor = SymmetricTwoportAdaptor(0.5, in1, in2)
out1 = Output(adaptor.output(0))
- out2 = Output(adaptor.output(1))
+ Output(adaptor.output(1))
with pytest.raises(ValueError, match="Duplicate output operation"):
SFG([in1, in2], [out1, out1])
diff --git a/test/test_signal_generator.py b/test/test_signal_generator.py
index b086ff069f98f863be3e73df0b90818aa2a7740e..787bf0d384d0c8d12be336d755c48d35c3743440 100644
--- a/test/test_signal_generator.py
+++ b/test/test_signal_generator.py
@@ -1,4 +1,3 @@
-import os
from math import sqrt
import pytest