From 767c7ea018e7e1e0cc2397ab427ffe868bf2f57b Mon Sep 17 00:00:00 2001
From: Mikael Henriksson <mike.zx@hotmail.com>
Date: Tue, 21 Mar 2023 16:15:57 +0100
Subject: [PATCH] correct parameters 'rows' and 'columns' in
generate_matrix_transposition()
---
.../streaming_matrix_transposition_tb.vhdl | 75 +++++++++++++++++++
b_asic/research/interleaver.py | 50 ++++++-------
test/test_resources.py | 15 ++++
3 files changed, 115 insertions(+), 25 deletions(-)
diff --git a/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl b/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
index 8267e356..eea5950b 100644
--- a/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
+++ b/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
@@ -100,6 +100,43 @@ begin
end architecture behav;
+--
+-- 4x8 memory based matrix transposition
+--
+library ieee, vunit_lib;
+context vunit_lib.vunit_context;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity streaming_matrix_transposition_memory_4x8_tb is
+ generic (
+ runner_cfg : string; -- VUnit python pipe
+ tb_path : string -- Absolute path to this testbench
+ );
+end entity streaming_matrix_transposition_memory_4x8_tb;
+
+architecture behav of streaming_matrix_transposition_memory_4x8_tb is
+ constant WL : integer := 16;
+ signal done : boolean;
+ signal input, output : std_logic_vector(WL-1 downto 0);
+ signal clk, rst, en : std_logic;
+begin
+
+ -- VUnit test runner
+ process begin
+ test_runner_setup(runner, runner_cfg);
+ wait until done = true;
+ test_runner_cleanup(runner);
+ end process;
+
+ -- Run the test baby!
+ dut : entity work.streaming_matrix_transposition_memory_4x8
+ generic map(WL=>WL) port map(clk, rst, en, input, output);
+ tb : entity work.streaming_matrix_transposition_tester
+ generic map (WL=>WL, ROWS=>4, COLS=>8) port map(clk, rst, en, input, output, done);
+
+end architecture behav;
+
--
-- 7x7 memory based matrix transposition
@@ -324,3 +361,41 @@ begin
generic map (WL=>WL, ROWS=>2, COLS=>2) port map(clk, rst, en, input, output, done);
end architecture behav;
+
+
+--
+-- 4x8 register based matrix transposition
+--
+library ieee, vunit_lib;
+context vunit_lib.vunit_context;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity streaming_matrix_transposition_register_4x8_tb is
+ generic (
+ runner_cfg : string; -- VUnit python pipe
+ tb_path : string -- Absolute path to this testbench
+ );
+end entity streaming_matrix_transposition_register_4x8_tb;
+
+architecture behav of streaming_matrix_transposition_register_4x8_tb is
+ constant WL : integer := 16;
+ signal done : boolean;
+ signal input, output : std_logic_vector(WL-1 downto 0);
+ signal clk, rst, en : std_logic;
+begin
+
+ -- VUnit test runner
+ process begin
+ test_runner_setup(runner, runner_cfg);
+ wait until done = true;
+ test_runner_cleanup(runner);
+ end process;
+
+ -- Run the test baby!
+ dut : entity work.streaming_matrix_transposition_register_4x8
+ generic map(WL=>WL) port map(clk, rst, en, input, output);
+ tb : entity work.streaming_matrix_transposition_tester
+ generic map (WL=>WL, ROWS=>4, COLS=>8) port map(clk, rst, en, input, output, done);
+
+end architecture behav;
diff --git a/b_asic/research/interleaver.py b/b_asic/research/interleaver.py
index 77763c02..3fdcd149 100644
--- a/b_asic/research/interleaver.py
+++ b/b_asic/research/interleaver.py
@@ -46,40 +46,40 @@ def generate_random_interleaver(
ProcessCollection
"""
- inputorder = list(range(size))
- outputorder = inputorder[:]
- random.shuffle(outputorder)
- inputorder, outputorder = _insert_delays(
- inputorder, outputorder, min_lifetime, cyclic
+ inputorders = list(range(size))
+ outputorders = inputorders[:]
+ random.shuffle(outputorders)
+ inputorders, outputorders = _insert_delays(
+ inputorders, outputorders, min_lifetime, cyclic
)
return ProcessCollection(
{
- PlainMemoryVariable(inputorder[i], 0, {0: outputorder[i] - inputorder[i]})
- for i in range(len(inputorder))
+ PlainMemoryVariable(inputorder, 0, {0: outputorders[i] - inputorder})
+ for i, inputorder in enumerate(inputorders)
},
- len(inputorder),
+ len(inputorders),
cyclic,
)
def generate_matrix_transposer(
- height: int,
- width: Optional[int] = None,
+ rows: int,
+ cols: Optional[int] = None,
min_lifetime: int = 0,
cyclic: bool = True,
) -> ProcessCollection:
r"""
Generate a ProcessCollection with memory variable corresponding to transposing a
- matrix of size *height* :math:`\times` *width*. If *width* is not provided, a
- square matrix of size *height* :math:`\times` *height* is used.
+ matrix of size *rows* :math:`\times` *cols*. If *cols* is not provided, a
+ square matrix of size *rows* :math:`\times` *rows* is used.
Parameters
----------
- height : int
- Matrix height.
- width : int, optional
- Matrix width. If not provided assumed to be equal to height, i.e., a square
- matrix.
+ rows : int
+ Number of rows in input matrix.
+ cols : int, optional
+ Number of columns in input matrix. If not provided assumed to be equal
+ to *rows*, i.e., a square matrix.
min_lifetime : int, default: 0
The minimum lifetime for a memory variable. Default is 0 meaning that at
least one variable is passed from the input to the output directly,
@@ -91,18 +91,18 @@ def generate_matrix_transposer(
-------
ProcessCollection
"""
- if width is None:
- width = height
+ if cols is None:
+ cols = rows
inputorder = []
- for row in range(height):
- for col in range(width):
- inputorder.append(col + width * row)
+ for col in range(cols):
+ for row in range(rows):
+ inputorder.append(row + rows * col)
outputorder = []
- for row in range(width):
- for col in range(height):
- outputorder.append(col * width + row)
+ for row in range(rows):
+ for col in range(cols):
+ outputorder.append(col * rows + row)
inputorder, outputorder = _insert_delays(
inputorder, outputorder, min_lifetime, cyclic
diff --git a/test/test_resources.py b/test/test_resources.py
index 582761e9..ea17a0b5 100644
--- a/test/test_resources.py
+++ b/test/test_resources.py
@@ -69,6 +69,21 @@ class TestProcessCollectionPlainMemoryVariable:
word_length=16,
)
+ def test_rectangular_matrix_transposition(self):
+ collection = generate_matrix_transposer(rows=4, cols=8, min_lifetime=2)
+ assignment = collection.graph_color_cell_assignment()
+ collection.generate_memory_based_storage_vhdl(
+ filename=f'b_asic/codegen/testbench/streaming_matrix_transposition_memory_4x8.vhdl',
+ entity_name=f'streaming_matrix_transposition_memory_4x8',
+ assignment=assignment,
+ word_length=16,
+ )
+ collection.generate_register_based_storage_vhdl(
+ filename=f'b_asic/codegen/testbench/streaming_matrix_transposition_register_4x8.vhdl',
+ entity_name=f'streaming_matrix_transposition_register_4x8',
+ word_length=16,
+ )
+
# Issue: #175
def test_interleaver_issue175(self):
with open('test/fixtures/interleaver-two-port-issue175.p', 'rb') as f:
--
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