diff --git a/b_asic/codegen/vhdl/architecture.py b/b_asic/codegen/vhdl/architecture.py
index 4f585f702c0d97f115052d0caafabffb7cae4b77..918718cd4b69983de96fe9ea4888641478e6f679 100644
--- a/b_asic/codegen/vhdl/architecture.py
+++ b/b_asic/codegen/vhdl/architecture.py
@@ -2,7 +2,7 @@
Module for code generation of VHDL architectures.
"""
from io import TextIOWrapper
-from typing import TYPE_CHECKING, Dict, Set, Tuple, cast
+from typing import TYPE_CHECKING, Dict, Iterable, Set, Tuple, cast
from b_asic.codegen import vhdl
from b_asic.process import MemoryVariable, PlainMemoryVariable
@@ -13,7 +13,7 @@ if TYPE_CHECKING:
def memory_based_storage(
f: TextIOWrapper,
- assignment: Set["ProcessCollection"],
+ assignment: Iterable["ProcessCollection"],
entity_name: str,
word_length: int,
read_ports: int,
diff --git a/b_asic/gui_utils/icons.py b/b_asic/gui_utils/icons.py
index 8ba60f4641ea0c3c26d68f69c34364081c407fcb..85fa6c818eafe920ef5e771d37a38f3086d96dc2 100644
--- a/b_asic/gui_utils/icons.py
+++ b/b_asic/gui_utils/icons.py
@@ -31,8 +31,8 @@ ICONS = {
'reorder': ('msc.graph-left', {'rotated': -90}),
'full-screen': 'mdi6.fullscreen',
'full-screen-exit': 'mdi6.fullscreen-exit',
- 'warning': 'fa.warning',
- 'port-numbers': 'fa.hashtag',
+ 'warning': 'fa5s.exclamation-triangle',
+ 'port-numbers': 'fa5s.hashtag',
}
diff --git a/b_asic/resources.py b/b_asic/resources.py
index a56bf32a8687c1a2d7dba6fa341364d65212dd32..4dbf57e16dbec117b47ea1fff749cad99e7fa840 100644
--- a/b_asic/resources.py
+++ b/b_asic/resources.py
@@ -2,7 +2,7 @@ import io
import re
from collections import Counter
from functools import reduce
-from typing import Dict, Iterable, List, Optional, Set, Tuple, TypeVar, Union
+from typing import Dict, Iterable, List, Optional, Tuple, TypeVar, Union
import matplotlib.pyplot as plt
import networkx as nx
@@ -84,7 +84,7 @@ def _sanitize_port_option(
raise ValueError(
f'Total ports ({total_ports}) less then write ports ({write_ports})'
)
- return (read_ports, write_ports, total_ports)
+ return read_ports, write_ports, total_ports
def draw_exclusion_graph_coloring(
@@ -209,12 +209,12 @@ class _ForwardBackwardTable:
ProcessCollection to apply forward-backward allocation on
"""
# Generate an alive variable list
- self._collection = collection
- self._live_variables: List[int] = [0] * collection._schedule_time
+ self._collection = set(collection.collection)
+ self._live_variables: List[int] = [0] * collection.schedule_time
for mv in self._collection:
stop_time = mv.start_time + mv.execution_time
for alive_time in range(mv.start_time, stop_time):
- self._live_variables[alive_time % collection._schedule_time] += 1
+ self._live_variables[alive_time % collection.schedule_time] += 1
# First, create an empty forward-backward table with the right dimensions
self.table: List[_ForwardBackwardEntry] = []
@@ -251,7 +251,7 @@ class _ForwardBackwardTable:
def _forward_backward_is_complete(self) -> bool:
s = {proc for e in self.table for proc in e.outputs}
- return len(self._collection._collection - s) == 0
+ return len(self._collection - s) == 0
def _do_forward_allocation(self):
"""
@@ -428,16 +428,16 @@ class ProcessCollection:
def __init__(
self,
- collection: Set[Process],
+ collection: Iterable[Process],
schedule_time: int,
cyclic: bool = False,
):
- self._collection = collection
+ self._collection = list(collection)
self._schedule_time = schedule_time
self._cyclic = cyclic
@property
- def collection(self) -> Set[Process]:
+ def collection(self) -> List[Process]:
return self._collection
@property
@@ -456,7 +456,9 @@ class ProcessCollection:
process : Process
The process object to be added to the collection.
"""
- self.collection.add(process)
+ if process in self.collection:
+ raise ValueError("Process already in ProcessCollection")
+ self.collection.append(process)
def remove_process(self, process: Process):
"""
@@ -962,9 +964,9 @@ class ProcessCollection:
-------
A set of new ProcessCollections.
"""
- process_collection_set_list = [set() for _ in range(max(coloring.values()) + 1)]
+ process_collection_set_list = [[] for _ in range(max(coloring.values()) + 1)]
for process, color in coloring.items():
- process_collection_set_list[color].add(process)
+ process_collection_set_list[color].append(process)
return [
ProcessCollection(process_collection_set, self._schedule_time, self._cyclic)
for process_collection_set in process_collection_set_list
@@ -1025,7 +1027,7 @@ class ProcessCollection:
)
for process, cell in coloring.items():
if cell not in cell_assignment:
- cell_assignment[cell] = ProcessCollection(set(), self._schedule_time)
+ cell_assignment[cell] = ProcessCollection([], self._schedule_time)
cell_assignment[cell].add_process(process)
return list(cell_assignment.values())
@@ -1066,7 +1068,7 @@ class ProcessCollection:
break
if insert_to_new_cell:
cell_assignment[next_empty_cell] = ProcessCollection(
- collection=set(), schedule_time=self._schedule_time
+ collection=[], schedule_time=self._schedule_time
)
cell_assignment[next_empty_cell].add_process(next_process)
next_empty_cell += 1
@@ -1139,7 +1141,7 @@ class ProcessCollection:
read_ports, write_ports, total_ports
)
- # Make sure the provided assignment (Set[ProcessCollection]) only
+ # Make sure the provided assignment (List[ProcessCollection]) only
# contains memory variables from this (self).
for collection in assignment:
for mv in collection:
@@ -1207,13 +1209,13 @@ class ProcessCollection:
A tuple of two ProcessCollections, one with shorter than or equal execution
times and one with longer execution times.
"""
- short = set()
- long = set()
+ short = []
+ long = []
for process in self.collection:
if process.execution_time <= length:
- short.add(process)
+ short.append(process)
else:
- long.add(process)
+ long.append(process)
return ProcessCollection(
short, schedule_time=self.schedule_time
), ProcessCollection(long, schedule_time=self.schedule_time)
diff --git a/b_asic/scheduler_gui/scheduler_item.py b/b_asic/scheduler_gui/scheduler_item.py
index 2f5f6eca176f60a19b876e4d0b7f40889515458d..66986c0a4fcd7bbbc41ee0649d860eb2d74341e4 100644
--- a/b_asic/scheduler_gui/scheduler_item.py
+++ b/b_asic/scheduler_gui/scheduler_item.py
@@ -139,10 +139,7 @@ class SchedulerItem(SchedulerEvent, QGraphicsItemGroup): # PySide2 / PyQt5
def _redraw_all_lines(self) -> None:
"""Redraw all lines in schedule."""
- s = set()
- for signals in self._signal_dict.values():
- s.update(signals)
- for signal in s:
+ for signal in self._get_all_signals():
signal.update_path()
def _redraw_lines(self, item: OperationItem) -> None:
@@ -150,6 +147,12 @@ class SchedulerItem(SchedulerEvent, QGraphicsItemGroup): # PySide2 / PyQt5
for signal in self._signal_dict[item]:
signal.update_path()
+ def _get_all_signals(self):
+ s = set()
+ for signals in self._signal_dict.values():
+ s.update(signals)
+ return s
+
def set_warnings(self, warnings: bool = True):
"""
Set warnings for long execution times.
@@ -162,10 +165,7 @@ class SchedulerItem(SchedulerEvent, QGraphicsItemGroup): # PySide2 / PyQt5
"""
if warnings != self._warnings:
self._warnings = warnings
- s = set()
- for signals in self._signal_dict.values():
- s.update(signals)
- for signal in s:
+ for signal in self._get_all_signals():
signal.set_inactive()
def set_port_numbers(self, port_numbers: bool = True):