diff --git a/b_asic/resources.py b/b_asic/resources.py
index 209c6b7966aadc81bb6b618f991dd90ad84f5f43..c8dd9c53f26a6052d7a74ba58a49fe4a9e7d1886 100644
--- a/b_asic/resources.py
+++ b/b_asic/resources.py
@@ -963,13 +963,14 @@ class ProcessCollection:
         total_ports : int
             The total number of ports used when splitting process collection based on
             memory variable access.
-        sequence: list of `Process`
+        sequence : list of `Process`
             A list of the processes used to determine the order in which processes are
             assigned.
 
         Returns
         -------
-        A set of new ProcessCollection objects with the process splitting.
+        list of `ProcessCollection`
+            A set of new ProcessCollection objects with the process splitting.
         """
 
         def ports_collide(proc: Process, collection: ProcessCollection):
diff --git a/examples/fivepointwinograddft.py b/examples/fivepointwinograddft.py
index 74051d2562b01f2c5ebe7010d0d19393a52ee715..3cbd921c59e338df7387c93172cac3fd9ff690a6 100644
--- a/examples/fivepointwinograddft.py
+++ b/examples/fivepointwinograddft.py
@@ -181,3 +181,17 @@ arch = Architecture(
 )
 
 arch
+
+# %%
+# Move memory variables to optimize architecture
+arch.move_process('addsub2.0', 'memory3', 'memory2')
+arch.move_process('bfly2.0', 'memory2', 'memory3')
+memories[2].assign()
+memories[3].assign()
+
+arch.move_process('cmul2.0', 'memory1', 'memory0')
+arch.move_process('bfly3.0', 'memory0', 'memory1')
+arch.move_process('bfly3.1', 'memory4', 'memory0')
+memories[0].assign()
+memories[1].assign()
+memories[4].assign()
diff --git a/examples/secondorderdirectformiir_architecture.py b/examples/secondorderdirectformiir_architecture.py
index a60c760d0149de36a6b6008933c0baa098f1b275..1a234a36b5f1b5bbe12deeaebc7c7eb3b3c065e5 100644
--- a/examples/secondorderdirectformiir_architecture.py
+++ b/examples/secondorderdirectformiir_architecture.py
@@ -98,43 +98,3 @@ arch = Architecture(
 # %%
 # The architecture can be rendered in enriched shells.
 arch
-
-# %%
-# To reduce the amount of interconnect, the ``cuml2.0`` variable can be moved from
-# ``memory0`` to ``memory2``.  In this way, ``memory0`` only gets variables from the
-# adder and an input multiplexer can be avoided. The memories must be assigned again as
-# the contents have changed.
-arch.move_process('cmul2.0', 'memory0', 'memory2')
-memories[0].assign()
-memories[2].assign()
-
-memories[0].show_content("New assigned memory0")
-memories[2].show_content("New assigned memory2")
-
-# %%
-# Looking at the architecture it is clear that there is now only one input to
-# ``memory0``, so no input multiplexer is required.
-arch
-
-# %%
-# It is of course also possible to move ``add3.0`` to ``memory2`` to save one memory
-# cell. It is possible to pass ``assign=True`` to perform assignment after moving.
-arch.move_process('add3.0', 'memory0', 'memory2', assign=True)
-
-memories[0].show_content("New assigned memory0")
-memories[2].show_content("New assigned memory2")
-
-# %%
-# However, this comes at the expense of an additional input to ``memory2``.
-arch
-
-# %%
-# Finally, by noting that ``cmul0.0`` is the only variable from ``memory1`` going to
-# ``in0`` of ``adder``, another multiplexer can be reduced by:
-arch.move_process('cmul0.0', 'memory1', 'memory2', assign=True)
-memories[1].show_content("New assigned memory1")
-memories[2].show_content("New assigned memory2")
-
-# %%
-# Leading to
-arch
diff --git a/examples/threepointwinograddft.py b/examples/threepointwinograddft.py
index aad3ddb23f5c4629255ca3c747f769cbb34e1d92..79bb7fb9037f737a42a6d26ce69672301392c560 100644
--- a/examples/threepointwinograddft.py
+++ b/examples/threepointwinograddft.py
@@ -57,6 +57,7 @@ sfg.set_execution_time_of_type(AddSub.type_name(), 1)
 schedule = Schedule(sfg, cyclic=True)
 schedule.show()
 
+# %%
 # Reschedule to only use one AddSub and one ConstantMultiplication per time unit
 schedule.set_schedule_time(10)
 schedule.move_operation('out0', 11)
@@ -88,6 +89,7 @@ schedule.move_operation('addsub2', -1)
 schedule.move_operation('addsub4', -4)
 schedule.show()
 
+# %%
 # Extract memory variables and operation executions
 operations = schedule.get_operations()
 adders = operations.get_by_type_name(AddSub.type_name())
@@ -123,7 +125,8 @@ for i, mem in enumerate(mem_vars_set):
     memory.assign("left_edge")
     memory.show_content(title=f"Assigned {memory.entity_name}")
 
-
+# %%
+# Create architecture
 arch = Architecture(
     {addsub, multiplier, pe_in, pe_out}, memories, direct_interconnects=direct
 )
@@ -131,7 +134,7 @@ arch = Architecture(
 arch
 
 # %%
-# Move memory variables
+# Move memory variables to reduce the size of memory1
 arch.move_process('addsub1.0', memories[2], memories[1])
 arch.move_process('addsub3.0', memories[1], memories[2], assign=True)
 memories[1].assign()