From 141cea8143c3d639ee41cada785fe3e49ec921fa Mon Sep 17 00:00:00 2001
From: Hugo Winbladh <hugwi268@student.liu.se>
Date: Mon, 3 Jul 2023 15:57:01 +0200
Subject: [PATCH] Fix code formatting for passing the pipeline
---
b_asic/architecture.py | 46 ++++++++++++++++++++++++++++++++-------
test/test_architecture.py | 5 +++--
2 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/b_asic/architecture.py b/b_asic/architecture.py
index 444ea6c3..18187871 100644
--- a/b_asic/architecture.py
+++ b/b_asic/architecture.py
@@ -172,7 +172,11 @@ class Resource(HardwareBlock):
def _digraph(self) -> Digraph:
dg = Digraph(node_attr={'shape': 'box'})
dg.node(
- self.entity_name, self._struct_def(), style='filled', fillcolor=self._color
+ self.entity_name,
+ self._struct_def(),
+ style='filled',
+ fillcolor=self._color,
+ fontname='Times New Roman',
)
return dg
@@ -193,11 +197,22 @@ class Resource(HardwareBlock):
ret = '<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">'
table_width = max(len(inputs), len(outputs), 1)
if inputs:
- in_strs = [f'<TD COLSPAN="{int(table_width/len(inputs))}" PORT="{in_str}">{in_str}</TD>' for in_str in inputs]
+ in_strs = [
+ f'<TD COLSPAN="{int(table_width/len(inputs))}"'
+ f' PORT="{in_str}">{in_str}</TD>'
+ for in_str in inputs
+ ]
ret += f"<TR>{''.join(in_strs)}</TR>"
- ret += f'<TR><TD COLSPAN="{table_width}">{self.entity_name}{self._info()}</TD></TR>'
+ ret += (
+ '<TR><TD'
+ f' COLSPAN="{table_width}">{self.entity_name}{self._info()}</TD></TR>'
+ )
if outputs:
- out_strs = [f'<TD COLSPAN="{int(table_width/len(outputs))}" PORT="{out_str}">{out_str}</TD>' for out_str in outputs]
+ out_strs = [
+ f'<TD COLSPAN="{int(table_width/len(outputs))}"'
+ f' PORT="{out_str}">{out_str}</TD>'
+ for out_str in outputs
+ ]
ret += f"<TR>{''.join(out_strs)}</TR>"
return ret + "</TABLE>>"
@@ -960,13 +975,28 @@ of :class:`~b_asic.architecture.ProcessingElement`
if len(source_list) > 1:
# Create GraphViz struct for multiplexer
inputs = [f"in{i}" for i in range(len(source_list))]
- ret = '<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">'
- in_strs = [f'<TD COLSPAN="1" PORT="{in_str}">{in_str}</TD>' for in_str in inputs]
+ ret = (
+ '<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0"'
+ ' CELLPADDING="4">'
+ )
+ in_strs = [
+ f'<TD COLSPAN="1" PORT="{in_str}">{in_str}</TD>'
+ for in_str in inputs
+ ]
ret += f"<TR>{''.join(in_strs)}</TR>"
name = f"{destination.replace(':', '_')}_mux"
- ret += f'<TR><TD COLSPAN="{len(inputs)}" PORT="{name}">{name}</TD></TR>'
+ ret += (
+ f'<TR><TD COLSPAN="{len(inputs)}"'
+ f' PORT="{name}">{name}</TD></TR>'
+ )
ret += f'<TR><TD COLSPAN="{len(inputs)}" PORT="out0">out0</TD></TR>'
- dg.node(name, ret + "</TABLE>>", style='filled', fillcolor=mux_color, fontname='Times New Roman')
+ dg.node(
+ name,
+ ret + "</TABLE>>",
+ style='filled',
+ fillcolor=mux_color,
+ fontname='Times New Roman',
+ )
# Add edge from mux output to resource input
dg.edge(f"{name}:out0", destination)
diff --git a/test/test_architecture.py b/test/test_architecture.py
index 9083a2a0..593fedc9 100644
--- a/test/test_architecture.py
+++ b/test/test_architecture.py
@@ -102,7 +102,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
+ '<TD COLSPAN="1" PORT="in1">in1</TD></TR>'
+ '<TR><TD COLSPAN="2">adder</TD></TR>'
+ '<TR><TD COLSPAN="2" PORT="out0">out0</TD></TR>'
- + '</TABLE>> fillcolor="#00B9E7" style=filled]\n}'
+ + '</TABLE>> fillcolor="#00B9E7" fontname="Times New Roman" style=filled]\n}'
)
assert adder._digraph().source in (s, s + '\n')
@@ -124,7 +124,8 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
+ '<TR><TD COLSPAN="1" PORT="in0">in0</TD></TR>'
+ '<TR><TD COLSPAN="1">MEM0</TD></TR>'
+ '<TR><TD COLSPAN="1" PORT="out0">out0</TD></TR>'
- + '</TABLE>> fillcolor="#00CFB5" style=filled]\n}'
+ + '</TABLE>> fillcolor="#00CFB5" fontname="Times New Roman" '
+ + 'style=filled]\n}'
)
assert memory._digraph().source in (s, s + '\n')
assert memory.schedule_time == 18
--
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