diff --git a/b_asic/architecture.py b/b_asic/architecture.py
index 18187871ad1848c38715cbf8fe7e2026141dac3c..dc78118a135ca79273735357943a3f6daebd6e2b 100644
--- a/b_asic/architecture.py
+++ b/b_asic/architecture.py
@@ -204,8 +204,8 @@ class Resource(HardwareBlock):
             ]
             ret += f"<TR>{''.join(in_strs)}</TR>"
         ret += (
-            '<TR><TD'
-            f' COLSPAN="{table_width}">{self.entity_name}{self._info()}</TD></TR>'
+            f'<TR><TD COLSPAN="{table_width}">'
+            f'<B>{self.entity_name}{self._info()}</B></TD></TR>'
         )
         if outputs:
             out_strs = [
@@ -987,7 +987,7 @@ of :class:`~b_asic.architecture.ProcessingElement`
                     name = f"{destination.replace(':', '_')}_mux"
                     ret += (
                         f'<TR><TD COLSPAN="{len(inputs)}"'
-                        f' PORT="{name}">{name}</TD></TR>'
+                        f' PORT="{name}"><B>{name}</B></TD></TR>'
                     )
                     ret += f'<TR><TD COLSPAN="{len(inputs)}" PORT="out0">out0</TD></TR>'
                     dg.node(
diff --git a/test/test_architecture.py b/test/test_architecture.py
index 593fedc9c060ff74a5a316613d60bbcde5a91a5d..108734b40b78be85cd791f06e8ae50935126b5c5 100644
--- a/test/test_architecture.py
+++ b/test/test_architecture.py
@@ -100,7 +100,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
         + ' [label=<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">'
         + '<TR><TD COLSPAN="1" PORT="in0">in0</TD>'
         + '<TD COLSPAN="1" PORT="in1">in1</TD></TR>'
-        + '<TR><TD COLSPAN="2">adder</TD></TR>'
+        + '<TR><TD COLSPAN="2"><B>adder</B></TD></TR>'
         + '<TR><TD COLSPAN="2" PORT="out0">out0</TD></TR>'
         + '</TABLE>> fillcolor="#00B9E7" fontname="Times New Roman" style=filled]\n}'
     )
@@ -122,7 +122,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
             + ' [label=<<TABLE BORDER="0" CELLBORDER="1"'
             + ' CELLSPACING="0" CELLPADDING="4">'
             + '<TR><TD COLSPAN="1" PORT="in0">in0</TD></TR>'
-            + '<TR><TD COLSPAN="1">MEM0</TD></TR>'
+            + '<TR><TD COLSPAN="1"><B>MEM0</B></TD></TR>'
             + '<TR><TD COLSPAN="1" PORT="out0">out0</TD></TR>'
             + '</TABLE>> fillcolor="#00CFB5" fontname="Times New Roman" '
             + 'style=filled]\n}'